1. Field of the Invention
The present invention generally relates to clock systems for computers and, more particularly, to a clock security ring for improved clock system error detection and a.c. fault isolation.
2. Description of the Prior Art
U.S. Pat. No. 4,800,564 to John J. DeFazio et al. describes a method and apparatus for testing a clock distribution network for a.c. and d.c. faults. The method described is suitable for use on computers with a latch scanning capability and provides a.c. and d.c. fault detection and d.c. fault isolation. The apparatus is illustrated in FIG. 1 and includes fault detection circuits 10 and 12, inverting delay circuits 14 and 16, and an error collection circuit 18. The error collection circuit 18 has several inputs, each of which is the output of one fault detection circuit. An arbitrary number of fault detection circuits may feed a single error collection circuit.
As described in the DeFazio et al. patent, the error collection circuit 18 detects the presence of a fault by determining if one of the fault detector outputs is in the opposite state of the other fault detector outputs. One possible implementation of the error collection circuit 18 is illustrated in FIG. 2 and comprises an Exclusive OR network of an even number of inputs. In this illustrative example, the Exclusive OR network comprises three Exclusive OR gates 22, 24 and 26, with Exclusive OR gates 22 and 24 receiving inputs from detectors A and B and from detectors C and D, respectively. The error collection circuit 18 has a single output from Exclusive OR gate 26 for rendering an error signal if a fault is detected.
The error collection circuit of FIG. 2 has a number of limitations. This error collection circuit will only detect some of the possible faults. The circuit renders an error output when one of the fault detector outputs is in the opposite state of the remaining fault detector outputs; however, the circuit will not render an error output in all cases where more than one of the fault detector outputs is in an incorrect state. For example, in the Exclusive OR network shown in FIG. 2, if the outputs of both detector A and detector B are in an incorrect state, then the error output will remain inactive.
In addition, because only a single error output is provided, it is not possible to determine which of the fault detectors is in an erroneous state, or even to determine some subset of the fault detectors as possibly in error. The DeFazio et al. patent describes a method for isolating d.c. (or stuck) faults, but not a.c. (or intermittent) faults.
An additional problem with the DeFazio et al. technique is that it is expensive to implement in large computing systems where fault detectors may be required on many chips. In this case, each of the fault detector outputs must be brought to some central point for error collection. In a system with, say, one hundred chips, each with one clock fault detector, the error collecting strategy described by DeFazio et al. requires one output per chip to report the fault detector states and one hundred chip inputs for error collection. A logic network which combined the one hundred fault detector outputs to determine if an error occurred would be large and could have substantial delay. No provision is made for dividing the fault detectors among several error collection circuits.